Zero Delay Buffers

Processor

A zero-delay buffer is a clock-distribution device that fans out a reference clock while using feedback, usually through a phase-locked loop, to align one or more outputs with the input reference. The term "zero delay" does not mean that physics has disappeared. It means the device is designed so the selected feedback output is phase-aligned to the input, canceling much of the apparent propagation delay through the buffer path.

Clock distribution matters because high-speed digital systems depend on timing margin. If a switch, router, server, base station, FPGA board, ADC/DAC system, or communications module receives clocks with too much skew, jitter, or phase error, setup and hold margins shrink. A clock tree that looks simple on a block diagram can become a source of intermittent failures across process, voltage, temperature, board routing, and load conditions.

What Zero Delay Means

A conventional fanout buffer receives one clock and drives several copies of it, but every output has propagation delay. A zero-delay buffer puts an output path into the PLL feedback loop. The PLL adjusts phase so the feedback clock edge lines up with the reference input edge. If the board routes and load conditions are designed carefully, the other outputs can be aligned closely to that same reference.

Analog Devices summarizes the idea well: in practical timing systems, relative edge alignment to a reference clock is what matters, so "zero delay" is appropriate when the output edge is aligned to the input reference after feedback compensation. Designers still have to account for residual phase offset, output-to-output skew, additive jitter, duty-cycle distortion, power-supply noise, layout, and load mismatch.

Timing Terms

Skew: timing difference between clock edges at different outputs or destinations.
Jitter: short-term variation of clock edge timing. It can be measured cycle-to-cycle, period, RMS, peak-to-peak, or integrated phase jitter depending on the application.
Phase error: the time difference between the reference edge and the aligned output edge.
Propagation delay: the time a signal takes to pass through a device or board trace.
Total timing budget: a combined allowance for several timing errors that affect whether the system still meets its margins.
Additive phase jitter: jitter contributed by the buffer or clock-distribution device beyond the jitter already present at its input.

The 2003 Cypress CY23020 Announcement

Cypress Semiconductor Corporation announced availability of two high-performance zero-delay buffers, the CY23020-1 and CY23020-3, featuring a guaranteed total timing budget window. The CY23020 clock-distribution devices were promoted as having an especially low total timing budget, combining maximum variation in jitter, output-to-output skew, and phase error. Cypress positioned them for switches, routers, base stations, and high-end servers.

As systems became more complex, the need for high-performance clock-distribution devices became more pronounced. Designers had to calculate timing error from separate data-sheet parameters such as skew, jitter, and phase error. The CY23020 family simplified this by specifying a single maximum total timing budget across variations in output frequency, supply voltage, operating temperature, input-edge rate, and process. The CY23020-1 featured a 335 ps maximum TTB, while the CY23020-3 provided a 400 ps maximum TTB.

"We've reduced user input to a single entry and minimized total timing budget impact by simplifying clock-tree design," said Tunc Cenger, marketing manager for Cypress's Timing Technology Division. "The CY23020 provides designers with a more accurate means of calculating TTB, which has led to significantly higher-performance clock schemes."

The CY23020-1 was a 200 MHz PLL-based zero-delay buffer for high-speed clock distribution. The CY23020-3 was a 400 MHz PLL-based zero-delay buffer with differential outputs and a 15 ps RMS jitter specification for communications applications requiring low noise. The CY23020-1 supported 50 to 200 MHz, while the CY23020-3 operated from 100 to 400 MHz. Both devices included options to multiply the reference clock by two and bypass the PLL for fanout-buffer use in system test mode, making the topic a chip-level cousin of broader network clock design.

What Changed Since 2003

Cypress Semiconductor became part of Infineon after Infineon completed its acquisition of Cypress in April 2020. Infineon's current clock and timing portfolio includes Cypress-branded buffers and other clock-distribution products, including non-zero-delay buffers, differential fanout buffers, and timing devices for automotive, industrial, computing, and communications systems.

The clocking problem also grew harder. Modern systems may need low-jitter clocks for PCI Express, Ethernet PHYs, radio transceivers, JESD204 data converters, FPGAs, SoCs, high-speed memory, image sensors, and precision measurement. In many of those systems, integrated phase noise matters more than a single peak-to-peak skew number. For RF data converters, software-defined radios, coherent optics, and high-speed SerDes, a clean clock can be as important as a fast clock.

When to Use a Zero-Delay Buffer

Several devices need the same reference clock with tight phase alignment.
Board-level propagation delay would otherwise consume too much timing margin.
A design needs both fanout and multiplication or selectable frequency behavior.
The system must align a distributed output back to an input reference or connector.
An FPGA, processor, switch ASIC, or communications device expects a low-skew external reference.

When a Different Clock Device May Be Better

A zero-delay buffer is not always the right answer. A plain fanout buffer may add less complexity when absolute phase alignment is not needed. A jitter cleaner may be better when the incoming reference is noisy. A clock synthesizer may be needed when several unrelated frequencies must be generated. A network synchronizer may be needed for telecom timing, SyncE, IEEE 1588, or holdover behavior. A low-phase-noise RF synthesizer may be required for radio or high-speed converter work.

Design Checklist

Decide whether the key requirement is phase alignment, low additive jitter, low skew, frequency synthesis, or jitter cleaning.
Read jitter specifications carefully. RMS jitter, cycle-to-cycle jitter, period jitter, and integrated phase jitter are not interchangeable.
Match output signaling to the loads: LVCMOS, LVDS, LVPECL, HCSL, CML, or another standard.
Route feedback intentionally. A zero-delay design only works as intended if the feedback path represents the delay you need to cancel.
Keep clock traces short, impedance-controlled, and length-matched where skew matters.
Use clean power. Power-supply noise can become clock jitter and phase noise.
Account for process, voltage, temperature, output loading, input slew rate, and board routing in the timing budget.
Measure the clock at the actual receiver or a representative test point, not only at the buffer pin.

Zero-delay buffers are small parts with large system consequences. They are valuable because they turn a messy clock tree into a more predictable timing structure, but they still require careful layout, feedback design, power integrity, and jitter budgeting.

Zero Delay Buffers - Yenra