Yenra : Networking : Zero Delay Buffers : High-Speed Clock Distribution

Processor

Cypress Semiconductor Corporation today announced availability of two high-performance zero delay buffers (CY23020-1 and CY23020-3) featuring a guaranteed total timing budget (TTB) window. The CY23020 clock distribution devices have the lowest TTB -- which embodies the maximum variation in jitter, output-to-output skew, and phase error -- of any comparable device on the market, making them ideal for use in switches, routers, Basestations and high-end servers.

As systems become more complex, the need for high-performance signal distribution devices becomes more pronounced. Designers are burdened with calculating the timing error from parameters listed in the data sheet including skew, jitter, and phase error. The CY23020 zero delay buffers reduce the burden by specifying a single parameter that guarantees a maximum TTB across variations in output frequency, supply voltage, operating temperature, input-edge rate, and process. The CY23020-1 features the industry's lowest TTB at 335 ps maximum, while the CY2303 provides 400 ps maximum TTB.

"We've reduced user input to a single entry and minimized total timing budget impact by simplifying clock-tree design," said Tunc Cenger, marketing manager for Cypress's Timing Technology Division. "The CY23020 provides designers with a more accurate means of calculating TTB, which has led to significantly higher-performance clock schemes."

The CY23020-1 is a 200-MHz PLL-based zero-delay buffer designed for high-speed clock distribution applications. The CY23020-3 is a 400-MHz PLL-based zero delay buffer with differential outputs and an aggressive jitter specification of 15 ps RMS, which makes it suitable for a variety of communication applications that require low noise. Both devices cover a wide range of communication and computation frequencies -- the CY23020-1 supports frequencies from 50 to 200 MHz while the CY23020-3 operates from 100 to 400 MHz. In addition, both CY23020 devices have options to multiply the reference clock signal by two and bypass the PLL to be used as fan-out buffers in system test mode.

Cypress Semiconductor Corporation is Connecting From Last Mile to First Mile with high-performance solutions for personal, network access, enterprise, metro switch, and core communications-system applications. Cypress Connects using wireless, wireline, digital, and optical transmission standards, including USB, Fibre Channel, SONET/SDH, Gigabit Ethernet, and DWDM. Leveraging its process and system-level expertise, Cypress makes industry-leading physical layer devices, framers, and network search engines, along with a broad portfolio of high-bandwidth memories, timing technology solutions, and reconfigurable mixed-signal arrays.