Packaging lithography forms features used to connect and protect semiconductor devices, such as redistribution patterns and openings for interconnects. The exposure must work with the substrate that actually arrives: its topography, distortion and die positions are part of the problem. Prepare the trial around the finished connection geometry.
Describe the pattern and the process route
Start with substrate format, material stack, carrier, pattern revision and the features that must connect. A redistribution layer reroutes electrical connections; its lithography may define a plating mold or another patterned layer within the chosen process. Document the subsequent transfer or plating steps so acceptance covers the final feature.
EV Group's maskless-lithography white paper discusses die-placement variation, die shift after molding and patterning challenges in fan-out packaging. Its tool-specific demonstrations illustrate why actual die positions and large-area pattern continuity matter; compare methods using your substrate and design.
Make the substrate condition measurable
On a narrow screen, scroll the table horizontally. Keyboard users can focus it and use the arrow keys.
| Input | What to record | Why it affects the trial |
|---|---|---|
| Topography and bow | Height variation, support and measurement locations | Coating coverage and exposure conditions vary across the substrate |
| Die position | Translation, rotation and residual distortion | Nominal layout coordinates may differ from real landing positions |
| Resist stack | Material, thickness, bake and development route | Profiles and feature clearing depend on the complete process |
| Alignment features | Location, visibility and underlying layers | The tool needs observable references for the required registration |
Coating and development deserve their own controls. Obtain current instructions for the actual resist and equipment; material changes can alter the useful exposure/development combination.
Connect overlay to the connection margin
Overlay describes registration between pattern levels or features. State whether the reported value is an axis component, a vector magnitude, an extreme value or a statistical measure, and retain its sampling locations. Compare residual overlay after the intended correction method with the actual geometry budget.
Fictional one-axis example: a 20 micrometre opening centered on a 40 micrometre pad has 10 micrometres of nominal margin on each side. A 6 micrometre offset leaves 4 micrometres on the nearer side. An 11 micrometre offset gives −1 micrometre, placing part of the opening beyond the pad. This simplified calculation omits size tolerances, the other axis and process variation; include them in a real acceptance budget.
Test a window, then inspect the transferred result
Sample center, edge and difficult topographic regions across representative substrates. Vary the applicable exposure and focus or mask-gap conditions through an agreed trial while controlling the other process steps. Measure feature dimensions, registration, resist profile and clearing using defined methods.
After the subsequent process, inspect the relevant final geometry and electrical continuity where required. Keep failures by location and type rather than averaging away an edge problem. Compare repeat runs and shifted or distorted substrates before releasing the operating window. Use the broader lithography guide to compare exposure families, then qualify the selected method on this package construction.
Use the working record
Download the editable packaging lithography trial. Save a copy, complete the actual requirements and evidence fields, and review open issues with the responsible owner. The plain-text record includes instructions, units where needed, the fictional example, and source references.