NAND flash supplies storage cells inside memory cards, USB drives, embedded storage and many SSDs. The finished product also needs control logic and firmware. To compare products, separate the cells’ organization from the interface, controller and workload that determine useful behavior.
Bits per cell and layers answer different questions
A cell encodes data through distinguishable electrical states. More bits per cell require more states. KIOXIA’s multilevel-cell explanation distinguishes this approach from stacking memory cells in layers.
On a narrow screen, swipe the table or focus it and use the arrow keys.
| Common name | Bits per cell | Required distinguishable states |
|---|---|---|
| SLC | 1 | 2 |
| MLC, in the usual two-bit usage | 2 | 4 |
| TLC | 3 | 8 |
| QLC | 4 | 16 |
The state count is 2 raised to the number of bits: four bits require sixteen patterns. A “3D TLC” description combines two facts: a layered cell arrangement and three bits per cell. Layer count alone says nothing about the finished drive’s usable capacity or sustained speed.
Increasing bits per cell can raise density while making electrical discrimination and programming more demanding. Product engineering manages those tradeoffs; compare the complete product’s documented endurance and performance. See 3D memory, HBM and stacked cache for the broader distinction between storage and stacked working memory.
Follow a write through the controller
A host asks to write logical addresses. The flash controller manages where that data lives physically. Micron’s NAND selection guide identifies error correction, bad-block management and wear leveling as essential management functions; a managed package includes a controller for this work.
NAND reads and programs pages, while erasure works on larger blocks. This difference is described in KIOXIA’s discussion of erase operations. Updating data can therefore require moving still-valid data and preparing space for later writes.
KIOXIA’s wear-leveling brief explains distributing write/erase activity across blocks. This reduces concentrated wear; it does not give every product the same lifetime. Firmware, spare area, error correction and the application’s behavior all belong in the evaluation.
Connect host writes to physical writes
Write amplification is the ratio of physical NAND writes to writes requested by the host. KIOXIA’s endurance technical brief explains the ratio and its relationship to NAND wear.
Read a complete product specification
- Identify the exact part and capacity. Specifications can differ within a named family.
- Record the interface and the test conditions behind sequential and random performance.
- Look for sustained writing after any fast buffer has filled, and test a representative workload.
- Read endurance definitions, operating temperature, retention conditions and health-reporting support.
- Check firmware support, power-interruption behavior and a recovery plan for the whole system.
A short burst can fit into a fast write buffer while a long capture reaches a different steady rate. High density may serve a mostly read collection well, but that observation does not choose a product for continuous logging. Evaluate the actual write pattern, capacity use and operating environment.
Retaining data while unpowered and tolerating repeated writes are related but separate requirements. Keep a backup and use model-specific retention guidance for archival or industrial designs. For packaged embedded storage, continue with iNAND and managed flash.