Extreme ultraviolet lithography patterns resist using light near 13.5 nanometres. Its useful performance comes from the complete chain: source, illumination, reflective mask, projection optics, resist and pattern transfer. Read any resolution or throughput claim with the pattern, process conditions and evidence that accompany it.
Follow the light and the pattern
ASML's explanation of lithography optics describes the move to reflective EUV optics. EUV light is strongly absorbed by ordinary optical materials and air, so mirrors and a vacuum environment replace a conventional refractive light path. Each optical surface and its condition affects the light that reaches the wafer.
The reflective mask carries the pattern. The projection system images it into a resist layer, where exposure and subsequent processing create a pattern that must survive transfer into the underlying stack. A clear resist image is one stage of that process; the final etched or deposited feature is the manufacturing outcome.
Look for a usable process window
On a narrow screen, scroll the table horizontally. Keyboard users can focus it and use the arrow keys.
| Claim | Conditions to request | What remains to demonstrate |
|---|---|---|
| Fine resolution | Pattern type, pitch, numerical aperture and mask | Acceptable dimensions and defects over representative features |
| Low exposure dose | Resist stack, development and inspection method | Roughness and stochastic-failure behavior |
| High throughput | Dose, exposure field, tool conditions and overheads | Repeatable accepted wafers under the production route |
| Successful demonstration | Sample size, test pattern, date and transfer steps | Qualification across actual product/process variation |
Imec's research explanation of stochastic failures describes random missing or bridging features and how the useful range depends on dose, pitch and materials. A small area with a good image cannot establish a sufficiently low failure rate for a much larger pattern population.
Compare dimensions, roughness and observed failures together. Record the inspected area or feature count and the detection method. Changing the resist, underlayer or transfer process can move the useful window; qualification belongs to the combined route.
Separate exposure time from complete throughput
Fictional timing model: exposure takes 2 seconds at one dose and 3 seconds at a dose 50% higher, assuming constant delivered power and exposed area. Add 5 seconds of other non-overlapping cycle work: the total rises from 7 to 8 seconds, or 14.3%, and idealized throughput falls by 12.5%. Real scanners pipeline operations and have further constraints. These numbers illustrate denominators, not equipment performance.
Request the dose and operating conditions behind a wafers-per-hour claim. Include repeatability, availability and downstream acceptance in a production comparison rather than extrapolating directly from source power.
Keep platform capabilities and adoption evidence distinct
ASML's EUV platform overview, checked October 2, 2026, distinguishes NXE systems from the EXE high-numerical-aperture platform, increasing NA from 0.33 to 0.55. It records the first High-NA system delivery in December 2023. Those platform facts establish neither universal adoption nor qualification of a particular customer's process.
Use dated manufacturer or customer disclosures for delivery, installation, acceptance and production status, naming which milestone was demonstrated. For context across other exposure methods, see modern lithography; for the different demands of package substrates, see packaging lithography.
Use the working record
Download the editable euv claim comparison. Save a copy, complete the actual requirements and evidence fields, and review open issues with the responsible owner. The plain-text record includes instructions, units where needed, the fictional example, and source references.