Semiconductor manufacturers and many suppliers have embraced advanced process and equipment control with an enthusiasm that could transform fab productivity within a few years, says a leading technologist from International SEMATECH (ISMT).
And that's just as well, adds Brad Van Eck, ISMT manufacturing methods project manager, because the industry's survival may depend on its ability to squeeze the last bit of uptime from equipment and near-perfect yield for wafers by using new data-collection systems organized by software yet to be written.
"It's all happening now, and we need it to happen fast," said Van Eck at the conclusion of the 15th Annual AEC/APC Symposium in Colorado Springs, CO. "The good news is that all chip makers are absolutely convinced that they need more real-time data for process and manufacturing equipment to improve fab productivity.
"No one even questions the fact that APC can be a cost avoidance tool and a productivity enhancement tool. Now the question is, 'When should I apply it, and how?' "
The symposium, held September 15-18, attracted more than 250 chipmakers, tool and software suppliers, and generated 72 technical papers that were presented in concurrent half-hour sessions. Dr. Mark Liu, vice president of operations for TSMC, delivered the keynote address, while both manufacturers and suppliers held tutorials.
The industry's acceptance of advanced equipment control (AEC) and advanced process control (APC) has been slow in coming, Van Eck said, because as recently as 1990, both were treated as esoteric pursuits outside the mainstream of manufacturing development. "There were a couple of prophets crying in the wilderness back then, but now we're all believers," he quipped.
Today, AEC/APC is advancing along three paths defined by a trio of proposed SEMI standards -- Equipment Interfaces A, B and C -- with each specifying sophisticated, in-tool software. Interface A would enable in-fab productivity improvement and would provide data for Interface C, which in turn would allow an offsite equipment-maker to monitor their tool's performance through an Internet connection. Interface B would permit tools and fab software applications to talk to one another, and potentially adjust processes already underway.
Van Eck expects Interface A to become an accepted standard by the end of this year, with commercial products from suppliers available in 2004. Interfaces B and C should be ready sometime next year, he added.
"These interfaces will make it very easy for third-party suppliers to install and maintain tool software, and for manufacturers to 'plug and play' them," Van Eck said. "This in turn will help generate data that eventually will make it possible to perform predictive maintenance, scrap avoidance, run-to-run control, and fault detection and classification.
"As a manufacturer, I will be able to see problems before they happen, and plan a solution for them. We will have made a huge leap forward."
Van Eck said the interfaces' data-mining capabilities, when coupled with interpretive programs that still need to be developed, will allow fabs to adjust tools and processes in the midst of production to maximize productivity.
That kind of precision, he added, will enable fabs to revolutionize their productivity, with such examples as:
- Customized processing. A wafer's interlevel oxide film deposition is slightly too thick. The error is caught by the deposition tool's integrated metrology and fault-detection system, which also determines that the error can be corrected during the subsequent chemical-mechanical polishing (CMP) step. The system then feeds forward this information to the correct CMP tool, which adjusts polish time for the wafer.
- Predictive maintenance. A tool is allowed to run for as long as it remains within process specifications, rather than being taken down for routine maintenance according to a fixed schedule. Also, wafers headed for a tool that sensors show will soon go down are rerouted well ahead of time, avoiding line delays.
- Accelerated requalification. A maintained or repaired tool is brought back on line by comparing its process "fingerprints" to that of a well- working system -- thus avoiding time-consuming punchlists.
- Reduced metrology time. Key process tools (especially lithography machines) have their own internal metrology functions, reducing the need to move wafers for metrical purposes. This saves volumes of money and process time, since in pre-APC days 30 percent of all wafer moves were to and from metrology tools.
"Moore's Law is not only about more chip features and thinner line widths, it's also about higher yield and higher equipment utilization to mitigate rising costs," Van Eck continued. "The biggest remaining piece of the profitability pie is now equipment availability -- squeezing more productivity out of every tool, and more chips out of every wafer. "Fortunately, the semiconductor industry now accepts this and is moving forward. Through the AEC/APC Symposia, we've been able to shave three or four years off the development cycle."
International SEMATECH (ISMT) is a global semiconductor technology development consortium that has effectively represented the semiconductor manufacturing industry on innovation issues since 1988. ISMT conducts state-of-the-art research, and is a highly-regarded technology partner whose goal is to promote the interests common to all chipmakers. It has extensive experience collaborating with equipment and materials suppliers, as well as government and academic research centers, to refine the tools and technology necessary to produce future generations of chips.