A phase-locked loop, or PLL, is a feedback system that adjusts an oscillator using the phase relationship between a reference and a returned signal. Frequency synthesizers use dividers in that loop to generate an output related to a stable reference.
A useful PLL choice starts with the required frequencies and what the receiving system tolerates: phase noise, timing jitter, unwanted spectral components and time to settle. The same output frequency can be produced by different divider plans with different performance and implementation costs.
Follow the loop one block at a time
- The reference supplies the starting clock. An input divider may reduce it to the phase/frequency detector rate.
- The phase/frequency detector compares that reference with the divided oscillator feedback.
- In a common charge-pump PLL, the detector and charge pump produce correction pulses. The loop filter shapes the resulting control signal.
- The voltage-controlled oscillator changes frequency in response to the control voltage.
- The feedback divider returns a scaled version of the oscillator signal for another comparison. An output divider may separately scale the delivered clock.
The locked condition keeps the average divided frequencies aligned and the phase error bounded. A real loop still has noise, ripple and transient behavior. Analog Devices’ PLL synthesizer tutorial explains the reference, feedback and fractional-divider architecture.
These blocks describe a common synthesizer architecture. All-digital PLLs and specialized clock devices can implement the correction differently. Use the part’s actual block diagram to decide which settings and equations apply.
Work through a frequency plan
A fractional-N design can produce a noninteger average feedback ratio. An illustrative N = 121.25 at a 20 MHz detector rate gives a 2,425 MHz oscillator. The actual device’s modulus, divider restrictions, spur behavior and calibration sequence determine whether that is a practical plan.
Check every stage, including minimum and maximum reference input, detector frequency, VCO tuning range and output-divider range. A mathematically correct frequency can still fall outside the hardware’s legal settings. Preserve the register configuration and the tool version used to produce it.
Keep noise and settling definitions explicit
On a narrow screen, scroll the table horizontally. Keyboard users can focus the table region and use the arrow keys.
| Quantity | What it expresses | Keep with the number |
|---|---|---|
| Phase noise | Spectral phase fluctuation relative to the carrier at an offset frequency. | Carrier frequency, offset in Hz, dBc/Hz value and operating condition. |
| RMS timing jitter | A time-domain uncertainty measure derived or measured over defined conditions. | Integration bandwidth or method, units and relevant clock path. |
| Spurs | Discrete unwanted spectral components. | Offset, level, divider plan and measurement settings. |
| Lock or settling time | Time until the output meets a stated condition after a change. | Starting/target frequencies, tolerance band, trigger and any calibration steps. |
Compare jitter figures over the same integration range and with the same relevant exclusions. A phase-noise value at one offset does not characterize the complete spectrum. ADI’s loop-optimization guidance distinguishes optimization for integrated jitter from a requirement at a specific offset.
Likewise, a digital lock indication is a device-defined detector result. Check whether the application needs a tighter frequency or phase-settling condition before releasing downstream logic.
Choose loop bandwidth around the noise sources
Loop bandwidth controls how the feedback responds to disturbances. Within the loop’s effective correction band, reference-path and detector-related contributions can be prominent; farther outside it, oscillator noise often becomes more important. The transition depends on the actual transfer functions and component models.
A wider bandwidth can accelerate response but also admits more reference-path noise or spurious content. A narrower loop can suppress some contributions while leaving more oscillator noise or slower settling. There is no single “lowest jitter” bandwidth independent of the reference, oscillator and application.
ADI’s phase-noise modeling article illustrates how reference, PLL and oscillator contributions enter a model. Use the selected part’s design tool and validated models, then confirm the result with measurements.
Loop-filter components, charge-pump current, VCO gain and supply noise all matter. Review component tolerance and layout along with the nominal filter calculation. Keep the manufacturer’s stability guidance and reference layout connected to the design.
Diagnose the missing condition
On a narrow screen, scroll the table horizontally. Keyboard users can focus the table region and use the arrow keys.
| Observation | Inspect first | Then verify |
|---|---|---|
| No lock indication | Reference present at correct level, enable/reset state, register write order and allowed divider plan. | Actual output spectrum and tuning/calibration status using the device procedure. |
| Locks at one frequency only | VCO band, tuning range, calibration and output-divider limits. | The complete requested frequency list across operating conditions. |
| Spurs exceed the target | Reference/charge-pump coupling, divider plan, supply behavior and measurement setup. | Changes one at a time with saved spectra and identical settings. |
| Clock is locked but system fails | Jitter band, amplitude, duty cycle, interface levels and downstream timing. | The clock at the receiving device and the system’s real acceptance condition. |
Retain the frequency plan, register file, loop-filter values, board revision and measurement method with every result. The worksheet turns “it locks” into a more useful statement: it reaches the required frequency and noise limits under a defined set of conditions.
Keep a working record
Download the phase-locked loops worksheet (editable text). Save a copy for each comparison or test. It includes the example assumptions, fields for source references and space for your results.