CMOS scaling is the work of fitting useful electronic functions into less space while managing power, speed, variability and manufacturing cost. A smaller technology label tells you which process generation is being discussed. To understand its value, look at what changed in the transistors, wiring and finished circuit.
This guide is for readers comparing semiconductor announcements or learning why transistor shapes changed. Start with the switch, then ask which measurement supports the claimed improvement.
Start with the transistor and the circuit
A field-effect transistor uses a voltage on its gate to control current through a semiconductor channel between source and drain. CMOS combines complementary n-channel and p-channel devices. In a simple inverter, a low input makes the output high and a high input makes it low. Real circuits also charge wiring and input capacitances, leak current, and dissipate heat.
Reducing dimensions can put more devices within a given area and shorten some connections. It also makes control harder: nearby electric fields influence the channel, small dimensional variations matter more, and wiring consumes part of the power and delay budget. The engineering task is to preserve a useful switch while integrating many switches into a reliable circuit.
Imec's CMOS scaling overview describes why progress combines device geometry, materials, patterning and circuit/system design. Its roadmap includes research directions; use dated manufacturing evidence when asking whether a particular process is available.
Why the gate wraps around the channel
On a narrow screen, focus this table and use the arrow keys to scroll.
| Geometry | How to picture it | Useful comparison |
|---|---|---|
| Planar | A channel near a flat surface, controlled principally from above. | Channel control, leakage and the process requirements for its intended application. |
| FinFET | A narrow upright fin with a gate covering its top and sides. | Drive current per footprint, fin count and variability. |
| Gate-all-around nanosheet | Several horizontal channels with gate material surrounding each sheet. | Sheet width and spacing, gate control and integration complexity. |
The important change is the gate's control over the conducting channel. A nanosheet is a semiconductor channel with a sheet-like shape; it does not imply a carbon-nanotube channel. Imec's nanosheet explanation describes the tradeoff between effective channel width, drive current and capacitance. Wider channels can carry more current, while their capacitance and required space also matter.
A schematic can hide the difficult work: releasing the sheets, forming a gate around them, making contacts and keeping device characteristics consistent. A working single transistor is one milestone. A circuit demonstration, manufacturing yield and a qualified product provide different evidence.
Read speed, power and area as a comparison
Ask what was held constant. A speed increase at a fixed power budget differs from a power reduction at a fixed speed. A density estimate for one standard-cell library differs from the transistor count divided by the area of a complete chip, which may contain memory, analog blocks and unused routing space.
For a product decision, compare the actual workload, memory configuration, cooling limits and sustained performance. For a process decision, ask about design rules, library assumptions, operating voltage, temperature and yield. Choose the evidence at the level of the decision you are making.
Separate names, dimensions and research directions
A modern node name is a process-generation designation. Actual gate length, contacted gate pitch and metal pitch are distinct dimensions. Write down the dimension and definition whenever an argument depends on a nanometre value. Likewise, the wavelength used in lithography and the dimensions of the resulting pattern describe different things; ASML's technology overview explains that different chip layers use different lithography systems.
Forksheet and complementary FET research explores further arrangements of devices. CMOS manufacturing techniques also support research into quantum devices. In each case, identify the actual device and demonstrated behavior: ordinary CMOS logic represents information through classical circuit states, while a qubit requires a specified physical quantum system and its control and measurement.
Save five facts with a scaling claim: the process and date; the structure changed; the metric and baseline; the test conditions; and whether the evidence is a simulation, fabricated device, circuit or production result. Those facts make a later update possible without guessing what a headline meant.
Related science guides
Explore all science guides. Sources reviewed September 11, 2026.