Integrated circuit design creates the electronic functions and physical structures manufactured on a semiconductor die. The work connects a specification with models, circuit implementations, layout, verification, packaging, and measurements on fabricated devices.
A chip project succeeds when the complete implementation meets its requirements. A clean simulation, a small layout, and an impressive clock frequency each describe only part of that outcome. Understanding the handoffs between stages makes design reports and tool demonstrations much easier to assess.
Map the work before choosing the tools
| Stage | Main question | Evidence carried forward |
|---|---|---|
| Specification and architecture | What must the chip do, under which conditions? | Interfaces, operating ranges, performance and power budgets. |
| Digital design | How will logic and state implement the behavior? | RTL, assertions, simulation results, and verification plans. |
| Analog and mixed-signal design | How will continuous signals be generated or measured? | Transistor-level circuits, models, and corner analyses. |
| Physical implementation | How will the design fit and connect on silicon? | Placement, routing, extracted parasitics, and timing reports. |
| Package and board integration | How will power, signals, and heat cross the die boundary? | Package models, pin assignments, and system constraints. |
| Silicon validation and production test | Does manufactured hardware meet the specification? | Measured results, test limits, and traceable configurations. |
Digital and analog design follow different paths
A digital flow commonly starts with register-transfer-level (RTL) logic. Synthesis maps that logic to cells in a library. Floorplanning, placement, clock distribution, and routing create a physical implementation that must be analyzed with the intended manufacturing process in mind.
The OpenROAD Flow user guide describes an open-source RTL-to-layout workflow and its component tools. It is a useful way to explore implementation stages. A completed flow run does not by itself establish that a design is ready for a particular foundry's fabrication process.
Analog design uses device-level behavior to meet requirements such as gain, bandwidth, noise, and matching. Layout can materially affect that behavior. Mixed-signal chips need verification of the interactions between analog circuits, digital control, clocks, and power states.
A process design kit (PDK) supplies process-specific models and design information. Standard-cell libraries, memory models, and verification rules must match the chosen process and supported flow. Files from unrelated technologies cannot simply be mixed because their formats look compatible.
Worked example: a timing budget that does not close
Possible changes include restructuring logic, improving placement, or adding a pipeline stage. A pipeline can alter latency and interface behavior, so its consequences belong in verification. Actual timing analysis must include the applicable clocks, exceptions, operating corners, and uncertainty.
Physical and package details are part of the circuit
Interconnect adds resistance and capacitance. Power delivery, clock distribution, thermal paths, and package connections can limit the system even when an isolated logic block looks satisfactory. Evaluate those interactions early enough to change the architecture.
Design-rule checking examines layout against geometric rules. Layout-versus-schematic checking examines connectivity against the intended circuit. Timing, power integrity, and reliability checks address additional requirements. None is a universal substitute for the others.
Preserve assumptions behind every result: tool version, models, corners, constraints, and input activity. Compare alternatives under the same conditions. A power estimate using an idle workload cannot fairly be compared with one using sustained activity.
Use automated assistance where results can be checked
AI can help draft verification cases, inspect repetitive reports, or explain unfamiliar flow settings. Give it the actual specification and documentation, then require citations to the records behind its conclusions. Treat proposed timing exceptions and model substitutions as engineering changes requiring review.
Review this synthetic design report against the supplied timing and latency requirements. Identify failed checks, unconstrained paths, and missing operating conditions. Distinguish measured, simulated, and estimated results. Do not interpret a completed tool run as design approval.
Where should a newcomer begin?
Build a small digital block with a written specification and independent tests. An FPGA implementation can help teach hardware behavior; an ASIC flow adds process-specific physical implementation concerns. For analog design, start with a circuit whose operating point and response can be calculated and measured.