iRoC Technologies announced today the release of M-BISTeR v2.0, a new SoC memory BIST platform dedicated to testing complex chips manufactured with nanometer processes. Detecting, diagnosing and repairing defects in embedded Memories are critical tasks to guarantee SoC Quality and Yield while managing design timeframe and silicon area. M-BISTeR v2.0 adds new SoC memory BIST management that enables managing several hundred memories per chip. Also new is BIST sharing that tests memories in parallel to save test time. Finally, v2.0 extends previous version features of RTL and On-Chip programmability, full diagnosis and Row/Column self-repair to a broader range of memory types that now include SRAM, Dual-Port RAM, ROM, CAM and DRAM. Designers will see an immediate benefit of less time designing complex tests on multiple memories because the tool automates these tests and enables more time to be spent on other SoC design tasks. This will assure higher quality chips and deliver more reliable products to market faster.
While switching to nanometer technologies offers more gain in performance, area and finally in profitability, it challenges design centers to maintain a similar time-to-market with more complex silicon issues of which SoC testability is critical. M-BISTeR v2.0 frees design engineers from having to program and manage complex features and options for embedded test. For example, it allows having only one test infrastructure hardware controller for hundreds of homogeneous memories. The product now is a shrink-wrapped integration of all new system-level features and capabilities from the previous version of M-BISTeR, simplifying design flow integration while maintaining the highest level of expertise, such as test algorithm programmability, full diagnosis, and word repair capabilities.
"To implement an optimized test strategy on a 90nm SoC today demands a high level of test expertise," stated Eric Dupont, president and CEO of iRoC Technologies. "By using M-BISTeR v2.0, design engineers have access to our cutting-edge expertise uniquely integrated in a very easy-to-use tool."
Usually the result of embedded test strategy choices is visible very late after the design is started and sometimes only with silicon die proving fault coverage accuracy. Even after sorting out dies that failed during the production test, it could still result in wrong dies signed off for shipment if BIST choices have not been thoroughly reviewed. This negative surprise will happen even more often if the design engineer is not working hand-in-hand with the foundry.
"Our recent experience on dual-port memories shows that test algorithms and their implementation have to be carefully chosen to get an acceptable quality and a profitable yield," stated Michael Nicolaidis, chief technical officer of iRoC. "We have seen end user returns that impaired the overall profitability of SoC projects of our customers."
Beyond the test of the memory instance, a test strategy at the system level needs to be carefully designed because embedding hundreds of memories on a SoC worsen a non-optimized local BIST consequence, causing more test complexity and more cost. Already providing the smallest commercial BIST IP in the previous version, the BIST sharing feature of M-BISTeR v2.0 enables to guarantee complete test simplicity and affordability. Usually grouped in a cluster per clock domain, memories are tested at-speed and the test is controlled with only very few pins connected to the ATE.
Because of its versatility and flexibility M-BISTeR will handle each type of memory, such as SRAM, DPRAM, ROM, DRAM, CAM or any other custom memory in order to ease and reduce test implementation time.
iRoC Technologies develops and licenses design and test solutions to enhance the quality, yield and reliability of nanometer integrated circuits.