A field-programmable nanowire interconnect, or FPNI, puts programmable nanoscale connections above CMOS logic. The central idea is to move much of the routing function into a dense upper layer while retaining conventional transistor circuits for logic. Judge that idea at both the routing and electrical levels.
Gregory Snider and R. Stanley Williams introduced this architecture in their 2007 Nano/CMOS architectures using a field-programmable nanowire interconnect paper. It was an architectural research proposal with modeled results. Its density and defect arguments are useful to examine as conditional engineering claims.
Locate the logic and the connections
CMOS stands for complementary metal-oxide-semiconductor. In the FPNI concept, CMOS cells provide logic functions, and programmable junctions in a crossed-wire layer connect the cells. Configuration determines which routes carry signals. This division differs from treating every nanoscale crossing as a logic gate.
A 2009 MITRE study by Adam Cabe and Shamik Das developed and simulated an FPNI implementation using 90 nm CMOS and 15 nm-wide nanowires. It found that junction behavior and customized CMOS circuitry mattered to correct operation. Its reported performance improvements were simulation results for the modeled designs and comparison baseline.
Draw three things separately when reading an architecture diagram: the logic cell, the programmable junction and the connection between layers. Then locate the configuration mechanism. This exposes which area and energy costs are included in a headline comparison.
A connected route must also carry a valid signal
The MITRE-authored full simulation paper examines finite resistance in both on and off junction states, including unwanted current paths. Its complete modeled design needed an on/off current ratio of at least 200 for correct behavior under the reported assumptions. That threshold belongs to the design and models studied, not to every possible crossbar.
For a proposed implementation, request waveforms at the receiving logic input as well as the routing map. State the supply, loading, wire resistance, capacitance and junction model. A map shows connectivity; valid voltage levels and timing show whether the receiving circuit can use the signal.
On a narrow screen, scroll the table horizontally. Keyboard users can focus the table region and use the arrow keys.
| Claim | Evidence needed | Boundary to record |
|---|---|---|
| Denser logic | Mapped circuits and counted area | Logic, routing, configuration and peripheral area |
| Lower energy | Comparable operation and energy measurement/model | Included circuits, activity and leakage |
| Faster operation | Electrical timing with realistic loading | Worst path, supply and device models |
| Defect tolerance | Fault model and successful remapping results | Fault types, locations and benchmark circuits |
| Working hardware | Fabricated circuit and measured outputs | Sample population and operating conditions |
Read defect tolerance as a routing problem
A broken wire removes a possible route. A short can create an unwanted connection. A junction stuck on behaves differently from one stuck off. A useful fault model says which of these occur, how locations are distributed and whether the mapping tool knows the defect locations before configuring the circuit.
Report success per attempted circuit mapping, with the circuit size, fault distribution and constraints. Random independent faults and a clustered damaged region can produce different outcomes. A percentage of defective elements alone is insufficient to reproduce a yield calculation.
Separate three levels of demonstration
- Architecture: identify the proposed functions and where they reside. Check that area estimates count the same boundaries on both sides.
- Simulation: identify models, parameters, benchmarks and failure criteria. Determine whether the result is logical mapping, electrical operation or both.
- Hardware: identify what was fabricated and measured. Ask how much of the complete architecture the sample contains and how many samples were tested.
A concrete review statement might be: “This model routed the listed circuits under the stated wire-break distribution; timing after rerouting still needs evaluation.” Another might identify a measured junction characteristic that supplies a model parameter. These statements make the next experiment clear without promoting a partial demonstration into a complete processor.
For background on programmable logic, use the FPGA guide. For the separate challenge of assembling semiconductor wires onto substrates, see nanowire films. The shared word “nanowire” can describe different materials and architectural roles.
Keep a working record
Download the nano cmos worksheet (editable text). Save a copy, fill in the fields for your situation and record exceptions as well as successful checks. The worksheet includes its purpose, source links and any example assumptions.