PLL — FREQUENCY PLAN AND VALIDATION
Use the exact synthesizer architecture and legal divider ranges. The examples are arithmetic
demonstrations, not register settings for a specific device.
Part / revision / reference source / design-tool version:
Reference frequency MHz / R / fPFD MHz = reference/R:
Feedback N (integer or fractional) / fVCO MHz = N*fPFD:
Output D / fOUT MHz = fVCO/D:
Illustrative: 40/2 = 20 MHz; 120*20 = 2400 MHz; D=2 -> 1200 MHz. N=121.25 -> 2425 MHz VCO at
20 MHz PFD.
Permitted reference/PFD/VCO/divider limits checked / source:
Target frequency list / step size / register files:
Phase-noise limits (carrier, offsets, dBc/Hz):
Jitter limit (rms time units, integration range, method):
Spur limits (offsets, levels, conditions):
Lock/settling tolerance / starting and target frequencies:
Lock detector definition and downstream enable rule:
Loop bandwidth / filter / charge-pump / VCO model / stability evidence:
Supply / temperature / board revision / measurement equipment:
Startup and frequency-hop results / spectra and timing files:
Unmet condition / one-variable change / retest:

Yenra | Updated September 10, 2026
Article and explanation: https://yenra.com/pll-phase-lock-loop/

Source references (use exact equipment/material documents for actual work):
https://www.analog.com/en/resources/analog-dialogue/articles/pll-synthesizers.html
https://www.analog.com/en/resources/faqs/faq_how_do_i_optimize_my_pll_loop_for_best_phase.html
https://www.analog.com/en/resources/technical-articles/system-level-lo-phase-noise-model-for-phased-arrays-with-distributed-phase-locked-loops.html