SiGe BiCMOS: Understand RF Integration and Device Tradeoffs
Yenra | Updated September 17, 2026
Article: https://yenra.com/ibm-thin-silicon-sige-bipolar-transistor/

Purpose: Compare SiGe/CMOS claims at matching conditions and separate measured results from projections.
Claim, source, publication date and baseline:
Evidence type: measured device / measured circuit / simulation / projection:
Process and device geometry:
SOI thickness or substrate details, if relevant:
Bias voltage/current, temperature and frequency:
fT / fmax definition and extraction method:
Noise, gain, linearity, bandwidth and load:
Power boundary, including bias/control blocks:
Example only: 1.8 V x 8 mA = 14.4 mW; 2.5 V x 5 mA = 12.5 mW. Compare functionality before interpreting the difference.
Historic distinction: IBM's 2003 paper reports measured 60/71 GHz peak fT cases on 120 nm SOI; its scaled-device result approaching 200 GHz was projected.
Conditions that match / conditions that differ:
Supported conclusion and missing circuit evidence:


SOURCE REFERENCES
IHP’s SiGe BiCMOS technology brochure
https://www.ihp-microelectronics.com/fileadmin/user_upload/Broschuere_MPW_IHP.pdf
2003 paper, Vertical SiGe-base bipolar transistors on CMOS-compatible SOI substrate
https://research.ibm.com/publications/vertical-sige-base-bipolar-transistors-on-cmos-compatible-soi-substrate
2004 follow-up on bipolar transistors on thin SOI
https://research.ibm.com/publications/bipolar-transistors-on-thin-soi-concept-status-and-prospect