HyperTransport: Link Width, Bandwidth and System Topology
Yenra | Updated September 17, 2026
Article: https://yenra.com/hypertransport/

HYPERTRANSPORT LEGACY-SYSTEM RECORD
Purpose: interpret documented and configured link capacity.
Processor/chipset/motherboard/firmware/OS:
Primary document URLs and revisions:
Endpoint A and endpoint B; intermediate hops:
Coherent/noncoherent role from the platform documentation:
Direction A->B: transfer rate GT/s, width bits, raw GB/s:
Direction B->A: transfer rate GT/s, width bits, raw GB/s:
Supported maximum versus configured operating point:

FORMULA: rate GT/s x width bits / 8 = decimal GB/s per direction.
2.0 x 16 / 8 = 4.0 GB/s.
5.2 x 16 / 8 = 10.4 GB/s.
Two symmetric 10.4 GB/s directions sum to 20.8 GB/s aggregate, while each remains 10.4 GB/s.
If starting from a clock, apply the documented transfers-per-cycle once.
ILLUSTRATIVE payload model: 4.0 GB/s x assumed 0.80 = 3.2 GB/s; 80% is not a protocol guarantee.

Workload, payload boundary, memory placement and measured result:
Other device/path limits:
Unresolved question and next read-only check:

SOURCE REFERENCES
Hammer-family BIOS and Kernel Developer’s Guide
https://www.amd.com/content/dam/amd/en/documents/archived-tech-docs/programmer-references/32559.pdf
AMD SR5650 Databook, revision 2.20 (2012)
https://www.amd.com/content/dam/amd/en/documents/archived-tech-docs/datasheets/47062.pdf
Family 10h and 12h software optimization guide
https://www.amd.com/content/dam/amd/en/documents/archived-tech-docs/software-optimization-guides/40546.pdf