Yenra Electronics

FPGAs in Production: Cost, Qualification and Change Control

Yenra — Mon, 18 Oct 2004 04:00:00 GMT

Compare programmable-logic production options using total cost, verification work, design-change flexibility and lifecycle evidence.

Published: 2004-10-18. Updated: 2026-09-17.

Optical S-Parameter Analysis: Loss, Phase and Measurement Confidence

Yenra — Tue, 03 Feb 2004 05:00:00 GMT

Plan passive optical-component measurements, define reference planes and interpret loss, phase, group delay and polarization results.

Published: 2004-02-03. Updated: 2026-09-17.

Spintronics: Electron Spin, Memory and Magnetic Sensors

Yenra — Fri, 08 Aug 2003 04:00:00 GMT

Connect spin-dependent resistance to memory and sensors, then compare switching, retention, endurance and energy claims at clear boundaries.

Published: 2003-08-08. Updated: 2026-09-17.

Custom Electronic Modules: Requirements and Supplier Acceptance

Yenra — Thu, 12 Oct 2017 04:00:00 GMT

Decide when a custom module is justified, define interfaces and measurable requirements, and plan ownership, production tests and lifecycle support.

Published: 2017-10-12. Updated: 2026-09-10.

Silicon Photonics: From Chip to Optical Link

Yenra — Mon, 28 Mar 2005 05:00:00 GMT

Follow light and data through a photonic chip, understand integration choices and evaluate the packaging, loss and power boundaries of an optical link.

Published: 2005-03-28. Updated: 2026-09-10.

High-Speed Board Connectors: Fit and Signal Integrity

Yenra — Mon, 31 Jan 2005 05:00:00 GMT

Choose a backplane or board connector by mechanical constraints, electrical paths and evidence for the complete assembled channel.

Published: 2005-01-31. Updated: 2026-09-10.

Digital Isolation: Signals, Power and Datasheet Ratings

Yenra — Wed, 24 Sep 2003 04:00:00 GMT

Map an isolation barrier, choose signal directions and power arrangements, and compare voltage ratings, timing and transient immunity.

Published: 2003-09-24. Updated: 2026-09-10.

Phase-Locked Loops: Frequency Planning, Jitter and Lock Time

Yenra — Tue, 03 Jun 2003 04:00:00 GMT

Follow a PLL feedback loop, calculate a frequency plan, and compare noise, timing and settling behavior with explicit measurement conditions.

Published: 2003-06-03. Updated: 2026-09-10.