EUV LITHOGRAPHY: HOW SOURCE, MASKS AND RESIST SHAPE THE PROCESS WINDOW
Editable planning/verification record — Yenra
Updated: October 2, 2026
Article: https://yenra.com/euv-lithography/

Purpose: Explain how EUV subsystems interact and read resolution, dose, defect and throughput claims with the conditions that make them meaningful.
Intended reader: Semiconductor students and technical readers trying to interpret EUV capability claims.

HOW TO USE
Save a working copy. Enter the actual specification, units, assumptions and evidence references in each field. Preserve original observations and record changes. Have the responsible reviewer resolve missing or conflicting requirements before release. Examples below are fictional teaching inputs, not process settings or acceptance standards.

RECORD
1. Claim, source, publication date and demonstrated versus planned status:
   ____________________________________________________________

2. Tool/platform, wavelength and numerical aperture:
   ____________________________________________________________

3. Pattern type, pitch, feature dimensions and mask conditions:
   ____________________________________________________________

4. Resist/underlayer stack, dose and development/transfer conditions:
   ____________________________________________________________

5. Critical dimension, roughness and stochastic-failure criteria:
   ____________________________________________________________

6. Inspected area or number of features, sampling and detection limits:
   ____________________________________________________________

7. Exposure time, overheads and complete throughput conditions:
   ____________________________________________________________

8. Comparability gaps, production qualification evidence and next source review:
   ____________________________________________________________


WORKED EXAMPLE AND LIMITS
Fictional timing model: exposure takes 2 seconds at one dose and 3 seconds at a dose 50% higher, assuming unchanged delivered power and exposed area. With 5 seconds of other non-overlapping cycle time, the complete cycle rises from 7 to 8 seconds, or 14.3%. Idealized throughput falls by 12.5% (7/8 = 0.875). Actual scanners pipeline operations and have other constraints; these inputs are teaching assumptions, not tool specifications or process settings.

REVIEW
Prepared by / date: ____________________
Reviewed by / date: ____________________
Open issues, responsible owner, due date: ____________________
Approved next action and evidence: ____________________

SOURCE CONTEXT
These primary references support the linked article. Use exact applicable product, contract, and document versions for operational work.
explanation of lithography optics
https://www.asml.com/en/technology/lithography-principles/lenses-and-mirrors
research explanation of stochastic failures
https://www.imec-int.com/en/imec-magazine/imec-magazine-july-2019/euv-lithography-sailing-along-the-stochastic-cliffs
EUV platform overview
https://www.asml.com/en/products/euv-lithography-systems

Return to the guide: https://yenra.com/euv-lithography/