Nano-CMOS Hybrids: Logic, Crossbar Routing and Defect Tolerance
Yenra | Updated September 17, 2026
Article: https://yenra.com/electr/nano-cmos.html

Purpose: Evaluate an FPNI or related hybrid-interconnect claim at architecture, simulation and hardware levels.
Paper / date / architecture name:
CMOS logic functions / nanoscale junction function / interlayer contacts:
Configuration mechanism and included peripheral circuits:
Area baseline and counted boundaries:
Wire/junction electrical models, supply and loading:
On/off behavior, leakage and receiver waveform evidence:
Fault types (break/short/stuck on/stuck off/other):
Fault distribution and whether locations are known to the mapper:
Benchmark circuits / mapping attempts / successes / timing criteria:
Alternative path and shared points of failure:
Measured hardware scope and sample count:
Supported conclusion / missing experiment:
Historical model boundary: MITRE's 2009 study modeled 90 nm CMOS with 15 nm-wide nanowires and found an on/off ratio of at least 200 necessary in that design. Do not treat it as a universal crossbar specification.


SOURCE REFERENCES
2007 Nano/CMOS architectures using a field-programmable nanowire interconnect paper
https://doi.org/10.1088/0957-4484/18/3/035204
2009 MITRE study by Adam Cabe and Shamik Das
https://www.mitre.org/news-insights/publication/performance-simulation-and-analysis-cmosnano-hybrid-nanoprocessor-system
MITRE-authored full simulation paper
https://www.mitre.org/sites/default/files/pdf/09_1082.pdf